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| Automatic Test Program GenerationTDX-ATG is a versatile and efficient ATPG program. It is a sequential test vector generator that you can use for full scan, partial scan or non-scan designs. It can generate vectors for synchronous or asynchronous circuits and for circuits with embedded RAM, bidirectional ports, and complex bus structures. TDX-ATG uses a variety of algorithms and techniques for analyzing netlists. For combinational portions of circuits, it employs the well-known PODEM and D algorithms. For sequential sections, it uses an extended backtrace method as well as proprietary forward-searching heuristics. TDX-ATG is tightly integrated with the TDX-FSIM fault simulator. TDX-FSIM provides accurate logic and fault simulation verification of generated vectors. This is important for circuits that: - use multiple clocks,
- are asynchronous, or
- have critical timing and bus resolution requirements.
The fault simulator employs a 23-state model with full timing support to verify that vectors generated by TDX-ATG actually detect the targeted fault. Integrating a sign-off quality fault grading tool into the tool set removes the element of surprise from the test generation process.
TDX-ATG and DFTTest vector generation for complex sequential circuits provides a considerable computational challenge for ATPG tools. TDX-ATG works harder than most to generate vectors whenever possible. Nevertheless, it is often necessary to reduce the task of vector generation in the interests of run time and vector set size. TDX-ATG works with TDX's testability profilers, TDX-TAP and TDX-STEP, to help users deal with complex sequential circuits by enhancing controllability and observability. Users can review and modify the DFT suggestions given by TDX-TAP and TDX-STEP, and add additional suggestions. Together, the two programs allow you to explore test strategies and generate efficient test vector sets, regardless of the amount of DFT modification you choose to apply to the circuit. "Virtual DFT" provides a quick and easy exploration of your vector generation options.
TDX-ATG OperationYou control TDX-ATG operation by a combination of command-line options, initialization files and run-time interaction. The command-line options can be supplied by means of a graphical user interface, called TDX Tool Manager. TDX-ATG takes a list of faults as input. This may be a subset of the full fault list, and may include faults detected by existing test vector sets. It also reads a file containing "seed vectors," if one is available. Typically, these are functional vectors that already detect a number of faults, and (prefereably) provide the reset sequence to initialize the complete circuit. In the absence of seed vectors, or if the seed vectors don't initialize all storage elements in the circuit, TDX-ATG identifies set or reset lines in the circuit and uses these to initialize the remaining storage elements. The primary actions of ATG are: - to sensitize each fault by justifying the signals that drive it to the correct values, and
- to propagate each fault effect to a point in the circuit where it is externally visible. This can be a primary output, a test point output (TPO) or a scan flip-flop.
If the circuit is sequential and does not have full scan, you needto justify circuit state over multiple time frames. When there are many sequential levels, this can be an involved and time-consuming process. TDX-ATG provides controls to limit the number of time frames and also the total time taken for the search. Dropping faults (at least temporarily) is often a good strategy, because the dropped fault may be found to be incidental to detection of another fault. |
