TDX-IDDQTDX-IDDQ is a fast, accurate and flexible implementation of the IDDq concepts developed for the Quietest program at Ford Microelectronics. It doesn't create new test vectors. It simply selects the best of a given set of vectors originating from the design verification process or generated by TDX-ATG. Before selecting a vectorTDX-IDDQ performs a complete examination of the state of the circuit to determine if the fault-free circuit might be drawing higher than normal current.
In addition to IDDq measurement, TDX-IDDQ also supports:
- Stuck-at coverage grading (results are merged with those of TDX-FSIM), and
- Toggle counting analysis
Detailed Fault Model
TDX-IDDQ models six potential faults per transistor for detailed measurement of device quality. The six faults are shorts between: - gate and source
- gate and drain
- source and drain
- bulk and source
- bulk and drain
- bulk and gate
Design cells are implemented with multiple transistors and have a correspondingly greater number of faults. For instance, an inverter has two transistors and twelve potential faults. Combinations of cell input values will detect some of these faults; others may be undetectable.
TDX-IDDQ comes with a pre-defined short model for each TDX primitive based on conventional CMOS cell implementation. Users may replace these models with their own to reflect actual foundry cell designs.
TDX-IDDQ reads fault models from ASCII text files of a simple format. The core of a cell definition is a sequence of input pattern definitions, followed by a list of faults detected by that pattern. Different parts of the circuit may use different transistor-level implementations of cells. The format allows you to specify a fault model specific to one or more instances matched by a wild-card pattern spec. (Wild-cards may match multiple hierarchy levels.)
Manual creation of fault models is tedious work. For this reason, TDX-IDDQ comes with a program that reads a transistor-level description of a logic gate or cell. The program first applies all pin states to the transistor model. It then performs a simulation to determine the steady-state value of each node in the cell. The program then looks at each transistor in the cell and determines if a short between any two terminals of the transistor would create a high-current path between VDD and GND. These shorts are detectable by current measurement, and are printed into the fault model definition. Since the resulting fault definition is a text file, it can be modified to dedicate it to one or more specific instances.
User-defined primitives (UDPs) have no obvious transistor-level implementation and IDDq fault model. To include these primitives in the results, it is necessary to supply a fault model for each one. This can be done by defining and analyzing a transistor-level implementation, as described in the preceding paragraph. In the absence of fault models for UDPs (or standard primitives), potential and detected faults are excluded from the results.
It is possible to add bridging faults between named pairs of nets into the fault model. A bridging fault is marked as detected when the nets are in opposite states (0 and 1 or 1 and 0, where both are actively driven).
Checking
Various checks are performed to ensure the basic requirements of IDDq are adhered to: - static design rule checking finds undriven nets and other problems not related to a defect
- dynamic rule checking ensures that an IDDq strobe does not occur when internal busses are not driven, when pull-up nets are driven to logic 0, etc.
Vector Selection
In a typical circuit, the first few current measurement strobes detect about 50% of transistor short faults. These strobes should be performed after the circuit is fully initialized, because TDX-IDDQ does not count detections when nets are unknown (X). After the first few strobes, it is advisable to be more demanding in strobe selection. A simple way to select strobe points is to only strobe if the new vector detects more than a specified percentage of previously undetected faults. TDX-IDDQ supports this approach.
TDX-IDDQ can also operate in a mode where it counts the number of faults detected by each vector, instead of marking the faults as detected. This analysis can be used to choose the most productive strobe points.
Perhaps the most effective vector selection mechanism provided by TDX-IDDQ uses toggle counting. Net toggle counts correlate well with fault detection, and are very efficient to process. The toggle selection algorithm takes the desired number of IDDQ strobes as a parameter and optimally selects that many strobe points. At the end of the run the selected strobe vectors are written to file and may be input to another IDDQ run to get accurate transistor-short fault coverage.
Summary
TDX-IDDQ uses the accuracy of the TDX simulation model to deliver detailed and accurate IDDq fault grading. Users have considerable flexibility in modeling their implementation of standard simulation primitives and UDPs. Several approaches are supported for selecting strobe vectors for measuring current consumption.
