TDX Fault Simulation TDX features a fast, full-timing fault simulation engine that simulates both Stuck-At Faults and transistor short faults detected by IDDq testing. In addition, your design can be logic simulated by the same engine to verify that your simulation performs as expected. PerformanceHardware-assisted fault simulation engines (such as Zycad's PXP) once had a decisive speed advantage for fault simulation. The availability of reasonably priced computers with extremely high instruction throughput and previously undreamed of memory sizes has caused a complete reversal of fortunes. Efficient software-based fault simulators running on advanced workstations now outperform hardware accelerators, and have lower acquisition and maintenance costs. TDX features a fast event-driven simulation engine. As a concurrent fault simulator, it keeps track of the state of the simulation under different fault conditions simultaneously. Efficiency in maintaining the state of faulty versions of the circuit (that is, circuit operation with particular nets hypothetically stuck-at 0 or 1) is crucial to simulator performance. TDX's efficient algorithm for managing this data has been refined to make better use of the cache architectures of advanced workstations significantly improving simulation performance. On some benchmarks a speedup of 3 to 10 times has been achieved, compared to other fault simulators. ControlTDX-FSIM is a high performance, affordable comcurrent fault simulator that grades test vectors on a wide range of state and timing sensitive circuits and circuits containing more than 1 million gates.
TDX-FSIM can be operated in three different modes:
- interactive mode
- batch mode
- distributed batch mode
In all three modes, command line options are used to identify the circuit to be simulated, the faultlist to process and various logic and fault simulation controls. In addition, an initialization file may be read to allow more detailed control of the simulation. For instance, this file may define input and trace vector formats, timeplates, fault detection options and memory management policies (e.g., when to give up on a fault that uses excessive memory). In interactive mode these commands may be typed directly to the simulator. Distributed Fault SimulationFault simulation is highly amenable to parallel processing on multiple computers. Previous versions of TDX supported parallel execution by supplying utilities to split a main faultlist into multiple subsets. After fault simulation, these subsets would be merged into a new master list. It is still possible to use this approach, but with TDX there is a much easier way to make full use of your computing power. TDX's stuck-at fault simulator, TDX-FSIM can be launched in distributed mode. In this mode, you give the fault simulator a list of UNIX host names and the number of faults to simulate on each host. You would probably assign a large number of faults to a powerful, state-of-the-art machine with lots of memory relative to a less powerful machine. TDX-FSIM then starts a simulation process on each of the nominated hosts and allocates the specified number of randomly selected faults to that simulation. When each simulation is complete, results are automatically merged back into the master fault list and another batch of faults is started on the host. Each host is repeatedly re-used until all faults have been processed. The graphical user interface, TDX Tool Manager, delivers a menu-based host selection mechanism for convenient configuration of a distributed fault simulation. It also keeps you informed of the progress of each host and of the overall simulation. Distributed fault simulation requires additional licenses for the second and subsequent simulation process. These secondary licenses are approximately half the cost of a primary simulation license. Distributed simulation, then, represents a cost-effective way of increasing fault simulation throughput. If only one simulation host is at your disposal, it can still be beneficial to run a number of smaller fault simulation jobs one after the other. The distributed simulation feature is available to do this even if you have no secondary simulation licenses.
Faultlist ManagementBefore you can run a fault simulation, you need a list of stuck-at faults to simulate (faultlist). TDX provides a utility to generate faultlists according to several different algorithms. It also allows a customized faultlist to be created. This can be useful, for instance, in targeting specific modules in the circuit. Equivalent faults are normally collapsed into one representative fault, enhancing fault simulation performance. Faultlists can be partitioned in various ways. Reproducible statistical samples of faults may be extracted. ReportingTDX Tool Manager can display a graph of fault coverage versus the number of applied vectors, and can update the display periodically as the simulation proceeds. You can generate detailed textual reports of fault simulation, with customized format and content. It's also possible to list faults based on various criteria (e.g., detection status, gate type, etc.). Fault Simulation and Design For TestOften, it's necessary to modify a circuit to achieve satisfactory test coverage. This can be because parts of the circuit are too difficult to control from the primary inputs, too difficult to observe at the primary outputs or both. Changing the circuit to address these difficulties is necessary; the problem is deciding which part, or parts, to change for acceptable coverage and minimal cost. TDX's fault simulators help you make this decision by supporting virtual DFT. An ASCII input file defines: - Test Mode Inputs (TMI), which enhance external control of the circuit
- Test Point Outputs (TPO), which enhance visibility of the internal nodes of the circuit
- Scan flip-flop chains (full or partial)
When supplied with this file, TDX fault simulators treat the circuit as if it had been modified to include these DFT features. Although it is possible to create the scan file with a text editor, the usual way is to run one of TDX's testability analyzers.
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