Design-for-TestMany circuits prove difficult to test comprehensively because of limited controllability and observability of internal nodes. Lack of external access to internal nodes can make Automatic Test Generation (ATG) impossible within the time constraints of current design cycles. The solution is to modify the circuit to address external access issues. Simple techniques to enhance accessibility are:
Test Mode Inputs, (TMI) test-specific input pins that enhance external control of the circuit Test Point Outputs, (TPO) test-specific output pins that make it possible to see the state of internal nodes.The alternative is to multiplex access to many points in the circuit using scan chains. In scan-chain operation, new states of nodes in the chain are scanned in sequentially. At the same time, information about the existing state of nodes in the chain is scanned out. For some circuits, it is feasible to replace all sequential elements (e.g. flipflops) with scan flipflops. This is known as full scan and dramatically simplifies ATG. For other circuits, full scan implementation is infeasible due to: - legacy cores,
- limits on die size, or
- minimum-speed requirements on particular paths.
In cases like these, it is normal to form a scan chain from some subset of the flip-flops in the design. This approach is known as partial scan. Even if your test strategy is to use full scan, the ability to exclude specific flip-flops from the scan chain provides valuable flexibility.
TDX Design-for-TestTDX features "Virtual DFT," which allows the software to perform as if the DFT features are present in the circuit — even though they have not actually been implemented — So you can explore different DFT strategies before choosing the one that proves most effective dramatically reducing turn-around time. Scan data may be incorporated into vector files. For example, a scan chain of eight elements gives rise to scan lines in the vector file with eight scan-in data values followed by eight "expected" scan-out values. In "virtual scan" mode, the scan operation is performed as a high-level parallel-load and unload of data. The operation takes place in one simulation vector machine cycle. This contrasts with an actual scan, where serial shift-in requires at least eight vectors. Thus, virtual scan enhances simulation throughput. TDX allows virtual scan parallel-load vectors to be automatically converted into serialized vectors that serially clock the data through the scan chain.
TDX addresses the full range of DFT issues: - TDX-STEP and TDX-TAP advise you on the best locations to add DFT circuit features;
- TDX-ATG creates vectors that utilize the DFT circuit features;
- TDX-FSIM and TDX-IDDQ analyze the effectiveness of the added DFT items;
- SCANMAKER implements the DFT recommendations.
Testability Analysis: TDX-STEP/TAP TDX-STEP/TAP is the only design-for-test tool that analyzes a circuits dynamic operation as well as its static topology to uncover testability problems. TDX-STEP/TAP uses SCOAP testability analysis numbers and various path tracing techniques to identify testability problem areas and find undetectable faults. It is also very useful in highlighting netlist and library translation problems. Plus TDX-STEP/TAP gathers information about fault-effect visibility by fault-simulating your design using your vector set. It also collects information related to unsensitized faults due to lack of controllability. The best use of TDX-STEP/TAP is to suggest locations for: Test Mode Inputs (TMIs), where coverage can be significantly increased by adding a test signal to enhance controllability, Test Point Outputs (TPO's), for nets in the circuit that capture a significant number of fault effects but are not currently propagated to output pins Storage elements that can be added to scan chains for partial scan. (For full scan, ALL storage elements are put in the chain.) TDX-STEP/TAP supports multiple scan chains. It also checks the circuit for scan rule violations. These are aspects of the circuit topology that make it impossible to load the scan chain without modifying the state of the rest of the circuit. Results of these suggestions are stored in text files for easy examination and modification. TDX-FSIM can read these files to enable "virtual DFT". SCANMAKER reads these files and implements the suggestions. TDX-STEP/TAP support even more advanced uses such as: - nets with low controllability
- nets with low observability
- uninitialized nets
- dead logic
- combinational loops
- undriven nets
- undetectable faults
- monostables
- cross-coupled latches.
In addition, interactive mode lets you trace specific paths forward or backward. The path trace can also list the SCOAP numbers along paths. TDX-ATG uses the results of TDX-STEP/TAP analysis to direct the efficient search for test vectors. DFT Implementation: SCANMAKERAfter you have verified your DFT strategy using the "virtual DFT" capabilities of TDX-FSIM and TDX-ATG, you need to implement your chosen features in your circuit. Doing this by hand is tedious and error-prone. Fortunately, help is at hand in the form the TDX's SCANMAKER program. SCANMAKER reads your Verilog source files, inserts the DFT features you have chosen, and writes out the modified circuit in Verilog. The circuit hierarchy and file layout (including comments) is preserved. For full-scan mode, the scan chain follows the circuit hierarchy; all the flip-flops in one module and the sub-modules it instantiates are connected before the chain exits the module. For partial scan mode, you can define the exact sequence of flip-flops in one or more scan chains. In conforming to your sequence, SCANMAKER may need to add multiple input and output connections to the module. You can set an option to minimize the number of entrances and exits to a module, which makes the partial-scan chains similar in style to the full-scan chains. SCANMAKER may need to duplicate modules to reflect different scan chain content or order in different instantiations. Typical circuits utilize a variety of storage cells (flip-flops, set-reset latches, etc). For each type of cell instantiated in the proposed scan chain, there must be an equivalent cell that supports the scan chain. SCANMAKER can handle multiple storage element types, as long as you advise it of the desired mapping between non-scan cells and their scan equivalents. SCANMAKER is closely integrated with TDX-STEP. TDX-STEP advises you about the modifications needed to repair scan rule violations and to achieve enhanced testability; SCANMAKER implements TDX-STEP's advice. The two programs are run separately and communicate via an intermediate text file. You can examine and modify this file to reflect your understanding of the circuit and any constraints for its implementation. | 
